• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The present invention relates to ultra-thin film-containing substrates and their use in laminates, circuits, interposers and other electronic laminates that are beneficial for the manufacture of high density circuits.
    公开号:KR20020011439A
    申请号:KR1020017016133
    申请日:2000-06-14
    公开日:2002-02-08
    发明作者:고든 스미스；제프리 티 고트로；마레 헤인；낸시 앰 더블류 안드로프
    申请人:크리스 로저 에이치；알라이드시그날 인코포레이티드；
    IPC主号:
    专利说明:

    High-density substrate and its manufacturing method {HIGH DENSITY SUBSTRATE AND METHODS FOR MANUFACTURING SAME}
    [2] The electronics industry has continually pursued increased product performance to meet the needs of consumers seeking higher functionality, lower cost computers and electronics.
    [3] The means available to the electronics industry to increase system performance is to design circuit boards with smaller, finer circuit lines and space.
    [4] Increasing the line density can reduce the number of circuit layers, resulting in smaller electronic devices. Fine forms are required not only for printed wiring board substrates but also for interposer applications in chip packages.
    [5] As the electronics industry is pursuing smaller surface mount packages with area array interconnect technology, routing I / O signals in the motherboard are becoming very challenging due to packaged fine pitch solderball connections.
    [6] As the solder ball pitch decreases, the escape circuits routed between the ball pads must be thin to maintain electrical isolation.
    [7] What does not meet this requirement is that they must be designed to use blind vias and the cost increases due to the large number of circuit layers.
    [8] Similarly, the surface mount chip package interposer itself presents a significant challenge. The ability to manufacture substrates capable of routing connection bonds or flip-chip connections over 1000 input / output will increase the escape routing constraints.
    [9] Without finer line formation, it would require more circuit layers and more cost to route from the die to the package solder balls.
    [10] Traditionally used in printed wiring boards and chip package interposers, the substrate consists of a glass-reinforced resin composite wrapped with a copper foil sheet. Laminates can be made by pressing a copper foil sheet into a glass cloth reinforcement resin. This copper foil serves as a seed layer for forming a circuit on the laminate surface.
    [11] Foils typically used for high density circuitry are electroplated films that have a rough surface for embedding "teeth" in the laminate to promote adhesion of the electroplated foil.
    [12] However, this rough surface has a problem that foil roughness and buried copper make it difficult to etch the circuit.
    [13] That is, it is difficult to etch copper between microcircuit traces because this roughness approaches the dimensions of the circuit.
    [14] In addition, longer and harsher etching conditions are required to completely remove the protrusions, which affects line quality. Therefore, there is a continuous need for alternative technologies that meet finer circuitry.
    [1] The present invention is directed to substrates used in the manufacture of high density circuits and to methods of using such substrates to produce laminates, circuits, interposers and other electronic laminates in fewer process steps compared to standard panelplate and pattern plate methods. It is about.
    [32] 1 is an exemplary cross-sectional view of a metal-clad laminate according to the present invention.
    [33] 2 is an exemplary cross-sectional view of another metal-clad laminate according to the present invention.
    [34] 3-6 is an exemplary cross-sectional view according to another embodiment of the present invention.
    [35] 7A-7K illustrate one embodiment of a pattern plating process including conventional steps unnecessary in the resulting process using the metal clad laminate of the present invention.
    [36] 8A-8K illustrate one embodiment of a simplified pattern plating process including conventional steps unnecessary in the resulting process using the metal clad laminate of the present invention.
    [37] 9A-9K illustrate one embodiment of a pattern plating process including unnecessary conventional steps as a result of using the metal clad laminate of the present invention.
    [38] 10 is a circuit cross section using a 5 μm foil as prepared in Example 11;
    [39] FIG. 11 is a circuit cross section using a 0.6 μm cladding as prepared in Example 11. FIG.
    [15] The present invention provides a method of making an electromagnetic plate using thin metal clad laminates.
    [16] The invention also includes an electromagnetic plate made from a thin metal clad laminate.
    [17] The present invention also includes a method of manufacturing an electromagnetic plate having a fine conductor.
    [18] In one aspect, the invention includes an electric substrate made of a metal clad laminate.
    [19] The substrate may include a carrier film, a release agent layer covering a surface of the film; And a conductive metal layer having a thickness of 10000 Pa or less, wherein the release agent layer includes a water-soluble polymer and may be mechanically peeled from the carrier layer.
    [20] In another aspect, the invention includes a method of forming at least one circuit trace on an electrical substrate using a metal-clad laminate. This method comprises a carrier film; A release agent layer covering the surface of the carrier layer and comprising a water soluble polymer and capable of being mechanically peeled from the carrier layer; And a conductive metal layer having a thickness of 10000 Pa or less; And attaching the metal clad laminate having the reinforced resin layer to form an electric substrate.
    [21] The carrier film is removed from the clad substrate. At least one via is introduced into the clad substrate, and a photoresist layer is applied to the surface of the clad substrate.
    [22] The photoresist layer is developed to expose the first conductive metal layer portion and to cover the second conductive metal layer portion after being illuminated.
    [23] The exposed first portion of the conductive metal layer and at least one via are electroplated with a conductive material. The remaining resist layer is removed from the metal clad laminate to expose the second portion of the conductive metal layer, and the metal clad laminate is flash etched to remove the exposed second portion of the conductive metal layer from the laminate.
    [24] In another aspect of the invention, the invention includes a method of forming at least one circuit trace on an electric substrate using a metal-clad laminate.
    [25] This method comprises a resin layer reinforced with a metal clad laminate comprising a carrier film, a release agent layer covering the surface of the carrier film and made of a water-soluble polymer and capable of being mechanically peeled from the carrier layer, and a conductive metal layer having a thickness of 10000 Pa or less. Bonding to the to form an electrical substrate.
    [26] At least one via is introduced into the clad substrate.
    [27] The carrier film is removed from the clad substrate and a photoresist layer is applied to the surface of the substrate.
    [28] The photoresist layer is exposed and then developed to expose the first portion of the conductive metal layer and cover the second portion of the conductive metal layer.
    [29] The first portion of the exposed conductive metal layer and at least one via are electroplated with a conductive metal.
    [30] The remaining resist layer is then removed from the metal clad laminate to expose the second portion of the conductive metal layer.
    [31] Finally, the clad laminate is flash etched to remove the exposed second portion of the conductive metal layer from the laminate.
    [40] The present invention relates to an ultra-thin metal conductive layer formed by depositing or sputtering a conductive metal on a polymer or metal carrier film coated with an organic polymer release agent.
    [41] This metal conductor layer can then be bonded to a printed wiring board substrate, such as an epoxy based laminate. The carrier film is then separated from the polymeric release agent and leaves a metal conductive layer adhered to the substrate. By using this method, a conductive metal layer in the range of 0.005 µm to 1.0 µm (50 to 10000 µs) can be used.
    [42] According to the present invention, a metal-clad laminate product for use in the manufacture of a printed circuit board is produced comprising a polymer or metal foil carrier layer, a polymer separation layer formed on the carrier film, and an ultra-thin metal layer formed on the release agent layer. Can be.
    [43] Shown in FIG. 1 is a metal-clad interlayer 10 made in accordance with the present invention. The intermediate layer 10 consists of a carrier layer 11, a polymer release agent layer 12 attached thereto and an ultra-thin conductor metal layer 13 attached thereto.
    [44] Shown in FIG. 2 is designated 20 as another example of such a metal clad laminate product.
    [45] According to the example of FIG. 2, the carrier film 21 is affixed to the polymer mold release agent layer or the separation layer 22. As shown in FIG.
    [46] The release agent layer 22 preferably has a second metal layer formed by sputtering or deposition.
    [47] 3 shows a carrier film 31, a release agent or separation layer 32 and a first ultra-thin conductor metal layer 33 as another example of the metal clad intermediate layer 30. The adhesive layer 35 is formed on the metal layer 33.
    [48] 4 includes a carrier film 41, a release agent layer 42, a first ultra-thin metal layer 43, a second metal layer 44, and an adhesive layer 45, as examples including the metal clad intermediate layer 4.
    [49] 5 shows a different metal clad intermediate layer 50, which includes a carrier film 51, a release agent layer 52, a first ultra-thin metal layer 53, and an adhesive layer 54. As shown in FIG.
    [50] The intermediate layer of this embodiment also includes two layers of circuit board resin laminate material, or pre-flags, which are labeled 56 and 57 here.
    [51] Shown in FIG. 6 is another metal clad-intermediate layer 60, comprising a carrier film 61, a release agent layer 62, a first metal layer, a second metal layer 64, an adhesive layer 65 and two resin laminate material layers 66 and 67.
    [52] These other examples are intended to illustrate the selection and number of various layers that can be used when assembling such intermediate layers.
    [53] Preferably, the carrier film is made of a flexible, dimensionally stable material having good durability and chemical resistance.
    [54] The carrier film must be able to withstand temperatures above ambient.
    [55] Preferably, the carrier film may have low water absorption and low residual solvent amount because water and solvent may be interrupted in the metallization step.
    [56] Suitable materials include polymeric films or metal foils.
    [57] Metal foils are preferred because of their high tensile strength, low water absorption, and low residual solvents at elevated temperatures.
    [58] The carrier film used in the examples below was an electroplated copper foil, a polyimide film or a polyester film. Metal foils from which other suitable carrier films are made are rolled or electrodeposited metals and alloys, including iron, aluminum (Allcoils) and copper (Gound Inc., Oak Mitsui 30 Inc.).
    [59] Certain polymer films are suitable for the practice of the present invention, and examples thereof include polyethylene terephthalate, polybutylene terephthalate and polyethylene naphthalate (Kaladex). , ICI, America), poly-propylene, polyvinyl fluoride (Tedlar DuPont polyimide (Kapton) , DuPont; Upilex UBE Industries and Nylon (Capran) , AlliedSignal).
    [60] A release agent layer (11 in FIG. 1, 21 in FIG. 2, 31 in FIG. 3, etc.) is used to facilitate removal of the carrier film from the ultrathin metal layer. In order to prevent picking problems caused by incomplete movement of the ultra-thin metal foil to the substrate, the release agent layer is designed to peel off the economic line between the separation layer and the film carrier layer. The separation layer is then removed using plasma, an oxidizing environment, strong light or a suitable solvent. Preferably it is washed with a solvent, more preferably with an aqueous solution to remove the layer.
    [61] In a method without a release agent layer and a method having a release agent layer that peels at the boundary between the separation layer and the ultra-thin metal layer, incomplete movement of the ultra-thin foil to a substrate occurs.
    [62] The separation layer (12 in FIG. 1, 22 in FIG. 2, etc.) is made of a polymeric material.
    [63] Preferably, this separation layer is a water soluble material to facilitate removal from the ultrathin metal layer.
    [64] Since the photoresist is formed in an alkaline atmosphere, it is most preferable to use a separation layer soluble in an aqueous alkali solution. Useful polymers are of good film-forming material.
    [65] The polymer is coated from water with the help of volatile bases such as ammonium hydroxide to improve solubility.
    [66] Optionally, the separation layer comprises a water soluble surfactant to improve solution wettability and to control dry defects.
    [67] As detailed in the Examples below, one useful release agent or separation layer is applied as a formulation comprising polyvinyl pyrrolidone (PVP), a surfactant and water.
    [68] The wet weight composition of the separation layer formulations described in the examples is 10% PVP and 0.5% surfactant.
    [69] In the practice of the present invention, 1% to 50% PVP and 0 to 5% surfactant are considered suitable.
    [70] Preferred PVPs for use in the present invention are those having a molecular weight of 10000 to 5,000,000.
    [71] In the practice of the present invention, acid-modified acrylic polymers, acrylic copolymers and polyesters, carboxylic acid functional styrene acrylic resins (SCJohnson Wax Joncryl) ), Polyvinyl alcohol (Air Products & Chemical, Arivol And release agents comprising polymers such as salourose-based polymers can be used.
    [72] Other suitable water soluble surfactants usable in the separation layer of the present invention are alkylaryl polyether alcohols (Rohm & Haas, Triton). , X100), Glycerin, Ethoxylated Castor Oil (Cas Chem Inc. Surfactols 365), and fluoro aliphatic polymer esters (3M Corporation, Fluorad 430).
    [73] The release agent layer formulation is applied in an amount sufficient to have a dry weight of 10 mg / ft 2 to 1000 mg / ft 2 and a thickness of 0.1 μm to 10 μm. Preferably, the release agent formulation is preferably in the dry weight range of 100 mg / ft 2 to 400 mg / ft 2 and thickness of 1 to 4 μm.
    [74] As described in the examples, a thin primary conductive metal layer (13 in FIG. 1, 23 in FIG. 2) is coated on the separation layer by sputtering using a Desk III (Denton Vacuum) or 903M (MRC) sputtering apparatus. Can lose.
    [75] Any kind of sputtering or deposition method known in the art may be used in the practice of the present invention. The first metal layer serves as a planting seed layer for subsequent circuit formation.
    [76] In the examples below, the metal layer was made of gold, chromium or copper. Examples of other suitable metals include tin, nickel, aluminum, titanium, zinc, chromium-zinc alloys, bronze, brass and alloys thereof. This metal layer can be made of a mixture of suitable metals. The first metal layer preferably has a thickness of 0.005 µm (50 µs) to 1.0 µm (10000 Angstroms), preferably 0.1 to 0.3 µm (1000 to 3000 µs).
    [77] Optionally, a second metal layer (24 in FIG. 2, 44 in FIG. 4 and 64 in FIG. 6) may be used to protect the first metal layer from oxidation and to increase adhesion during lamination or as a barrier against metal migration. .
    [78] The second metal layer may have a thickness of 0.001 (10 μs) to 0.19 μm (1000 μs), and most preferably, 0.01 μm (100 μs) to 0.03 μm (300 μs). To form the second metal layer, a layer of zinc, iron, tin, cobalt, aluminum, chromium, nickel, nickel-chromium, bronze or brass is deposited on the first metal layer.
    [79] Other suitable metals include magnesium, titanium, manganese, bismuth, molybdenum, silver, gold, tungsten, zirconium, antimony and chromium-zinc alloys.
    [80] The second metal layer prevents the first metal from being oxidized after being removed from the metallization chamber and increases adhesion to the thermosetting resin system.
    [81] Optionally, an adhesive layer (35 in FIG. 3, 45 in FIG. 4) may be formed in the metal layer. This adhesive layer is intended to increase the bond between the metal layer and the substrate layer after lamination.
    [82] The bonding layer may be an organic, organometallic or inorganic compound and is applied with a thickness of 0.0005 μm (Å) to 10 μm (100000 μm).
    [83] Multiple layers may be used, such as an organometallic layer and an organic layer. When an organometallic layer such as silane is used, the coating layer will have a thickness of 0.0005 μm (5 μs) to 0.005 μm (500 to 100000 angstroms).
    [84] When using organic adhesive layers such as thermoplastics, thermoset polymers or mixtures thereof, the coating layer will have a thickness of 0.1 μm (1000 μs) to 10 μm (100000 μs).
    [85] Useful organometallic compounds include zirconium, titanium, and silicon based materials.
    [86] Silicone-based organometals known as silanes or binders are widely used. This binder can be used as such or dissolved in a suitable solvent. Suitable binders typically have alkoxy, acyloxy or amine functional groups and organic functional end groups.
    [87] The hydrolyzable end groups react with the metal surface while the organofunctional group is attached to the substrate layer on which the metal is laminated.
    [88] The binder undergoes hydrolysis prior to coating upon dissolution in the acid medium. Useful binders include compounds such as N- (2-aminoethyl) -3 amino propyltrimethoxysilane (Dow Corning, Huls America Inc.) and 3-glycidoxypropyl trimethoxy silane (Dow Corning, Huls America Inc.) Can be mentioned
    [89] The organic adhesive layer which consists of a thermoplastic, a thermosetting polymer, or a mixture thereof is a suitable adhesive layer.
    [90] These adhesives may be polyimide resins, epoxy resins, polyester resins, acrylic resins, butadiene rubbers.
    [91] One adhesive consisting of a polyester epoxy system is available (Cortaulds, Z-Flex ). The resin layer may be applied to a metal layer or an adhesive requiring dielectric thickness control. Such uses include building technology.
    [92] Typically these resins are thermosetting resins coated from a suitable solvent. After drying, these resins can be cured in a semi-cured state if additional curing is required before lamination to the circuit board.
    [93] One semi-cured resin layer can be used. Preferably two layers are used so that the first resin layer is cured to a greater extent than the second resin layer. The first resin layer serves as a controlled dielectric space layer and has a thickness of 5 to 500 mu m, preferably 20 to 50 mu m. Examples of suitable resin systems include epoxy resins, cyanate esters, bismaleimide and polyimide systems cured with phenol or dicyanidiamide curing agents.
    [94] The second resin layer has a composition different from that of the first resin layer, but in order to obtain good interlayer adhesion, the composition of the second resin layer is preferably similar to that of the first resin layer. The second main layer serves as an adhesive layer and as a pore layer during the lamination and has a thickness of 5 to 500 m, preferably 20 to 50 m.
    [95] "Laminating under appropriate lamination conditions" means laminating under appropriate time and pressure conditions for a suitable time to bond the layers together for practical use in the manufacture of circuit board laminates.
    [96] The metal clad laminate of the present invention is beneficial for the production of various types of electronic substrates. The laminate is also useful for the manufacture of double-sided layer pairs useful as single-sided rigid substrates and chip package interposers.
    [97] For example, one or more laminates can be combined to make a multilayer printed wiring board.
    [98] Laminates of the present invention are typically combined with technical components by various plating processes, such as panel plating and panel plating processes, with or without vias in the substrate during manufacture. In fact, the laminates are preferably used in panel and pattern plating processes to produce multilayer electrical substrates.
    [99] The use of the laminate of the present invention in a pattern plating process can reduce many process steps in conventional processes.
    [100] 7-9 summarize the new panel and pattern plating process using the laminate of the present invention.
    [101] Each process starts with the clad substrate 100.
    [102] The clad substrate 100 includes a carrier film layer 1 facing each other, a release agent layer 102, a conductive metal layer 103, an optional second metal layer 104, and an optional adhesive layer 105. These layers are each combined with a resin reinforced core layer 107 and the two resin reinforced layers adhere to each other to form a core 107.
    [103] In step 7B, the carrier film 101 is removed from the clad substrate and the release agent layer 102 is removed to expose the ultrathin conductive metal layer 103 in step 7C as described above.
    [104] Via 110 is formed in the cradle substrate 100 by a drill or a laser. Unlike conventional processes, photoresist 111 is applied to the cover through the ultra-thin conductive metal layer 103 and via 110.
    [105] In step 7F, the photojelist is exposed and developed to create an exposed first portion of the ultra thin conductive metal layer 103 corresponding to the circuit pattern 112 and a covered second portion of the ultra thin conductive metal layer 103.
    [106] In step 7G, via 110 is electroplated with the exposed circuit trace to form an electroplated layer 114.
    [107] 7H shows a prior art step in which an etch resist is typically applied to the required circuit trace. However, since the ultra thin conductive metal layer 103 is so thin, the remaining resist layer may be removed in step 7i to expose the second portion 115 of the ultra thin metal layer 103 and the clad substrate may be flash etched in step 7J to expose any exposed built-in of the metal plate 103. The non-up site can be removed.
    [108] The flash etching is performed by coating commercially available etchant such as spray, dipping, persulfate or ferrous chlorides.
    [109] Flash etching step 7J also eliminates the prior art step shown at 7K, including excluding the etch resist that was applied to the circuit trace in prior step 7H.
    [110] The flashetch product shown in FIG. 7J is a layer, pair comprising a first circuit 116 and a second circuit 116 ′.
    [111] 8 shows a pattern plating method using the laminate of the present invention to reduce the number of process steps required to produce a laminate comprising one or more circuit traces.
    [112] The process of FIG. 8 is identical to the process of FIG. 7 except that the release agent layer 103 is not removed in step 8C as in step 7C.
    [113] Instead via 110 is drilled into the clad substrate in step 7D, a photoresist is applied in step 7E and exposed in step 7F.
    [114] Exposure and development of the photoresist expose the first portion 112 of the ultra-thin conductive metal layer 103 corresponding to the circuit trace by removing the separation layer portion corresponding to the photoresist portion removed.
    [115] Via 110 and circuit traces are electroplated in step 8G. In step 8 the step of applying etch resist is omitted and the remaining separation layer is removed in step 8i to expose the second portion 115 covered by the metal layer 103. Finally, the exposed second portion 115 of the metal layer 103 is flash etched from the substrate containing the necessary electronic traces.
    [116] 9 shows a pattern plating-drill enhancement process of the present invention using the metal clad substrate of the present invention.
    [117] The main aspect of this process is step 9b, in which via 110 is drilled or lasered into the clad substrate 100 without removing the carrier film layer 101 or the release agent layer 102.
    [118] Once via 110 is formed in substrate 100, carrier film layer 101 and release agent layer 102 can be removed as in steps 9C and 9D.
    [119] Photoresist is then applied to the ultra-thin conductive metal layer 103 and exposed and developed to form circuit traces in steps 9E and 9F.
    [120] The circuit trace and via 110 are electroplated with a conductive metal in step 9G. At this time, it is not necessary to add a separate etch resist as required by the conventional method. Instead, the resist is peeled off and the substrate is flash etched to remove metal layer 103 and any other second metal layer and adhesive layer 105.
    [121] The following examples are merely examples of the present invention, and the present invention is by no means limited.
    [122] Example 1
    [123] Upilex from Ube Industries for use as a carrier film 50 micrometers (1500 micrometers) was purchased. After copper sputtering of 0.15 μm (1500 μs), the nickel-chromium alloy was coated with 0.01 μm (100 μs).
    [124] This sample was pressed to make a circuit board laminate. Teflon glass-reinforced four layers of FR-4 pre-preg, known as FR 406 (AlliedSignal) Placed on the sheet.
    [125] Under the sheet was a stainless steel press plate.
    [126] The structure was placed on the FR 406 prepreg with the metal side down.
    [127] Second glass-reinforced Teflon The sheet layer was placed on top and covered with a second stainless steel press plate. The load was placed in a preheated press at 350 ° F. and pressed at 50 psi for 1.2 hours.
    [128] The film was to be peeled off, but it was very difficult. Peel strength was measured at 180 degrees and was 1-5 lb / in. Metal coating sites having a thickness of 100 μm remained on the film. This was done twice and it was judged that the metal film did not peel off from the film carrier. The metal fixation force on the film was strong enough to tear the film during the peeling attempt.
    [129] Example 2
    [130] A 1 oz sample of copper foil electroplated for use as a carrier film was obtained from Gould Inc. No. A release layer was formed by coating the separation layer formulation P1 (Table 1) on a copper carrier layer using an 18 lead-wound rod.
    [131] After applying to the carrier film, the release agent layer was dried at 160 ° C. for 2 hours. The film was transparent.
    [132] Air was used as the process gas and a gold conductive layer was sputtered onto the transparent separation layer using a Desh III sputtering apparatus.
    [133] Gold was deposited for 3 minutes. When the edge of the gold film was examined under a microscope, a gold layer with a thickness of 0.3 µm (3000 mm) was attached.
    [134] The sample was pressed to make a circuit board laminate.
    [135] Four layers of FR-4 epoxy based prepreg, known as FR 406 (AlliedSignal), are glass reinforced Teflon. It mounted on the sheet.
    [136] Underneath the sheet was a stainless steel press plate. The structure was placed face down on the FR 406 pre-preg. 2nd glass reinforcement Teflon The sheet layer was placed on top of it and covered with a second stainless steel plate.
    [137] The load was placed in a press preheated to 350 ° F. and pressed for 1.2 hours at 50 psi.
    [138] After cooling to room temperature, the copper carrier film was easily peeled off and the separation layer fell off completely with the metal film. The surface was washed with warm water to remove the release agent layer and showed a shiny metal surface.
    [139] Composition of Separator Layer Blend P1 ingredientsauceQuantity Polyvinylpyrrolidone PVP-K90ISP Technologies5.00 g Surfactol 365Cas chem0.025 g water 44.975 g
    [140] Example 3
    [141] Gould Inc. for use as a carrier film. An electroplated copper foil of 1.0z was obtained from
    [142] No. Formulation P1 (Table 1) was coated onto the copper carrier film using an 18 lead-wound rod to form a release agent layer. After application to the release agent layer, the separation layer was dried at 160 ° C for 2 hours. The film was transparent. The mold release layer was dried at 160 ° C. for 2 hours. The film was transparent. The gold conductive layer was sputtered on the transparent separation layer using a Desk III sputtering apparatus using air as a process gas, and gold was deposited for 3 minutes.
    [143] Examination of the edge of the gold film under a microscope showed that a gold layer of about 0.3 μm (3000 mm) was formed.
    [144] The sample was pressed to make a circuit board laminate. Teflon glass-reinforced four layers of FR-4 epoxy-based pre-plexes known as FR 406 (AlliedSignal) Placed on the mount. The sheet bottom part was a stainless steel press plate. The structure was placed face down on the FR 406 prepreg.
    [145] 2nd glass reinforced Teflon The sheet layer was placed on top and covered with a second stainless steel pressplate.
    [146] The load was placed in a pre-heated press and pressed at 50 psi for 1.2 hours at 350 ° F.
    [147] After cooling to room temperature, the copper carrier film was easily peeled off and the separation layer was transferred completely with the metal film and resin layer. The surface was washed in warm water to remove the separation layer and showed a shiny metal surface.
    [148] Composition of Resin Blend R1 ingredientsauceQuantity (g) Epon 1031A 70Shell chemical1.98 DER 732Dow Chemical5.67 PKHS-40Phenoxy associates18.16 Ciba 1138A85Ciba geigy15.91 Quatrex 6410Dow Chemical22.69 BT 2110Mitsubishi Gas & Chemical34.97 DMF 7.37 Methyl ethyl ketone 46.13
    [149] ingredientsauceQuantity (g) Polyvinylpyrrolidone, PVP-K120ISP Technologies5.00 Surfactol 365Cas chen0.25 water 44.975
    [150] This formulation P2 differs from that of PVP K120 with a weight average molecular weight of 2,900,000.
    [151] PVP used in the blend P1 was PVP K90 with a weight average molecular weight of 1,270,000.
    [152] Higher molecular weights are advantageous for coating and film formation, while lower molecular weights are advantageous because of increased layer solubility.
    [153] Example 4-7
    [154] 1/2 oz samples of high temperature stretched copper foil electroplated for use as carrier films were purchased from Oak-Mitsui.
    [155] The carrier film was coated with release agent formulation P2 using a No 18 lead- wound rod and dried at 160 ° C. for 2 minutes. The coating was transparent and 250 mg / ft 2 .
    [156] Different metal layer combinations were sputtered onto the P2 film using argon as the process gas.
    [157] Metal layerRemarks Example 43000, Gold (Angstrom)Example 5Chromium, 100 to 200 mmExample 6Copper 3000Å then Chrome 100ÅA thin chromium layer is used as the passivation layer between the copper and the laminate. Example 7Copper 1500Å then Zinc 50 ~ 100ÅA thin zinc layer is used as the passivation layer between the copper and the laminate. When the structure is heated under pressure, zinc is alloyed with the thin copper layer to form brass.
    [158] The structure is of the type illustrated in FIG. 1.
    [159] An adhesive layer made of silane was coated on the metal films of Examples 6 and 7.
    [160] Gamma- glycidoxypropyl trimethoxy silane solution was prepared at 0.5% in a 90:10 mixture of methanol and water. The solution was coated on the metal surface and dried at 90 ° C. for 1 minute.
    [161] Each sample was pressed to make a circuit board laminate.
    [162] Glass-reinforced Teflon four layers of FR-4 pre-preg, known as FR 406 (AlliedSignal) Placed on the sheet.
    [163] Under the sheet was a stainless steel pressplate.
    [164] The structure was placed on a FR 406 pre-preg with the metal side down.
    [165] 2nd glass reinforcement Teflon The sheet layer was placed on top and covered with a second stainless steel press plate.
    [166] The load was placed in a preheated press at 350 ° F. and pressed at 50 psi for 1.2 hours.
    [167] After cooling to room temperature, the copper carrier film was easily peeled off and the separation layer was transferred completely with the metal film. The surface was washed with hot water to remove the separation layer and the shiny metal surface of the conductive layer appeared.
    [168] Peel force required to remove the carrier layer was measured in Examples 6 and 7 at 180 ° angles. The measurement result was very low. Example 6 was 0.025 lbs / in and Example 7 was 0.015 lbs / in.
    [169] Example 8
    [170] Upilex from Ube Industries A 50 μm polyimide film was purchased.
    [171] No. Separation layer formulation P2 was coated on the carrier film using an 18 lead-wound rod and dried at 160 ° C. for 2 hours. The coating was transparent and 250 mg / ft 2 .
    [172] The gold conductive layer was sputtered on the transparent separation layer using air as a process gas and using a Desk III sputtering apparatus.
    [173] Gold was deposited for 3 minutes. When the edge of the gold film was examined under a microscope, a gold layer having a thickness of about 0.3 µm (3000 mm) was attached.
    [174] The sample was pressed to make a circuit board laminate.
    [175] Four layers of FR-4 epoxy based prepreg, known as FR 406 (AlliedSignal), are glass reinforced Teflon. It mounted on the sheet.
    [176] Underneath the sheet was a stainless steel press plate. The structure was placed face down on the FR 406 pre-preg. 2nd glass reinforcement Teflon The sheet layer was placed on top of it and covered with a second stainless steel plate.
    [177] The load was placed in a press preheated to 350 ° F. and pressed for 1.2 hours at 50 psi.
    [178] After cooling to room temperature, the copper carrier film was easily peeled off and the separation layer fell off completely with the metal film. The surface was washed with hot water to remove the separation layer and showed a shiny metal surface.
    [179] Example 9
    [180] Upilex for use as a carrier film 50 μm polyimide film was purchased from Ube Industries.
    [181] No. The release blend P2 was coated onto the carrier film using an 18 lead-wound rod and dried at 160 ° C. for 2 hours. The coating was transparent and 250 mg / ft 2 .
    [182] A copper metal layer was vapor deposited on the transparent film using a CVE vacuum chamber of CVC Product, Inc.
    [183] Copper was attached for 4 minutes. An adhesive layer composed of silane was coated on the metal layer.
    [184] Gamma glycidoxy fluorophyll trimethoxy syran was prepared at 0.5% in a 90:10 mixture of methanol and water. The solution was corned on a metal surface and dried at 90 ° C. for 1 minute.
    [185] The sample was pressed to make a circuit board laminate.
    [186] Four layers of FR-4 epoxy-based flap, known as FR 406 (AlliedSignal), are glass reinforced Teflon. It mounted on the sheet.
    [187] Underneath the sheet was a stainless steel press plate. The structure was placed face down on the FR 406 pre-preg. 2nd glass reinforcement Teflon The sheet layer was placed on top of it and covered with a second stainless steel plate.
    [188] The load was placed in a press preheated to 350 ° F. and pressed for 1.2 hours at 50 psi.
    [189] After cooling to room temperature, the copper carrier film was easily peeled off and the separation layer fell off completely with the metal film. The surface was washed with warm water to remove the release agent layer and showed a shiny metal surface.
    [190] The peel force required to remove the carrier layer was very low at 0.010 lbs / in as measured at 180 ° C. and was highly repeatable.
    [191] Example 10
    [192] Using as a Carrier Film A 1/2 oz sample of high temperature stretched copper foil electroplated was obtained from Oak-Mitsui.
    [193] No. The release mixture P2 was coated onto a copper cairter layer using an 18 lead-wound rod and dried at 160 ° C. for 2 hours. The film was transparent and the measurement result was 250 mg / ft 2 .
    [194] CVC Products, Inc. A copper metal layer was deposited on the transparent coating layer using a product CVE vacuum chamber.
    [195] Copper was deposited for about 4 minutes.
    [196] The sample was pressed to make a circuit board laminate. Four layers of FR-4 prepreg, known as FR 406 (AlliedSignal), are glass reinforced Teflon. It was placed on a sheet and covered with a second stainless steel pressplate.
    [197] The load was placed in a pre-heated press and pressed for 1.2 hours at 50 psi.
    [198] After cooling to room temperature, the copper carrier film was easily peeled off and the separation layer fell off completely with the metallization.
    [199] The surface was washed with hot water to remove the separation layer and showed a shiny metal surface.
    [200] Example 11
    [201] A 2 mil thick polyester film was purchased from DuPont for use as a carrier film.
    [202] The release separation layer formulations shown in Table 4 were prepared and coated onto films using conventional coating techniques. After drying at 100 ° C. for about 2 minutes, the film was transparent.
    [203] The coated film was then metallized in a continuous film sputtering system and attached to 6000 Pa of copper followed by 100 Pa of chrome passivation.
    [204] This metallized ultrathin structure was made into the sheet form, and lamination was produced.
    [205] Composition of Separation Layer ingredientsauceQuantity Polyvinylpyrrolidone, PVP-K120ISP Technologies500.0 g Surfactol 365Caschem2.5g water 4497.5 g
    [206] The metallized structures were compared with a 5 μm electroplated copper foil supplied on a 72 μm thick copper foil carrier available from Circuit Foils.
    [207] The 5 μm foil, which was an electroplated foil, had a rough surface with protrusions embedded into the laminate.
    [208] Ultrastable from AlliedSignal Laminate System Prepregs were used by each cladding to make laminates.
    [209] The foil was laminated to the prepreg under heat and pressure to form a double-sided clad substrate having a total thickness of 200 μm (8 mils).
    [210] Pattern plating technology was used to design circuits on each cladding with 2 mil lines, 2 mil spaces, and 6 mil through holes in 14 mil pads.
    [211] A very thin clad laminate was prepared by removing the polyester cover sheet and washing the separation layer in hot water, showing a clean copper surface.
    [212] The copper foil cover sheet was removed to prepare a 5 μm clad substrate.
    [213] Each substrate was perforated by techniques known in the art to form a 6 mil yield.
    [214] Each substrate was then passed through conventional desmear and electroless chemicals to clean for electroplating and seed the hole walls. Negative dry film photoresist was laminated to each substrate, exposed and developed, showing negative.
    [215] Each substrate was electroplated to form circuit traces and pads.
    [216] The resist was stripped and the cladding layer was flash etched to form isolated traces and pads.
    [217] Sub micron cladding and 5 μm electroplated copper foil were processed through platers and resist strips.
    [218] However, the differences were evident when monitoring each process.
    [219] The panel was periodically passed through an etchant, removed and studied by light microscopy.
    [220] Etching continued until no foot appeared in the circuit base and the background between lines became metallic.
    [221] Panels using 5 μm copper foil increased the etching time by 60% compared to sub-micro technology.
    [222] Each factor is frequently monitored in the printed wiring board field to assess circuit quality. Etch elements are measured by taking a circuit cross section and measuring the height and width of the trace.
    [223] From these measurements the etch factor is calculated by dividing the circuit height by the trace width at the base compared to the circuit face.
    [224] Etch elements are calculated using other equations.
    [225]
    [226] Where T is the width of the circuit trace at the top
    [227] B: width of herotrace base
    [228] t is the circuit trace height.
    [229] Most circuit patterning processes produce circuits with etching elements 2.5-3.5.
    [230] Higher quality circuits with straight circuit walls have larger etching elements.
    [231] 5 micron foil was used to compare the quality of the circuit trace to the sub-micro technology. After etching, the circuits were cross sectioned. The circuit was inspected using an optical microscope and the etch elements were measured.
    [232] 10 and 11 show typical circuits obtained with 5 μm foil and sub-micron cladding.
    [233] Traces made of bus-micro copper had a vertical line with little slope. However, the 5 μm sample had a relatively short line height and inclined line side walls.
    [234] This difference is obtained because, in 5 micro copper, longer etching time is required to remove the embedded teeth by etching through the thicker seed layer.
    [235] The etching elements were measured for each cladding and are shown in Table 5. Higher quality sub-micron samples have been shown to be very impressive with an etching element of 8.0 in this example.
    [236] Circuit line qualityIndustry standard5㎛ foil0.6㎛ cladding Etching elements2.5 to 3.51.78.0
    权利要求:
    Claims (19)
    [1" claim-type="Currently amended] Carrier film;
    A release agent layer covering the surface of the carrier film, comprising a water-soluble polymer, and capable of being mechanically peeled off from the carrier film (RELEASE AGENT LAYER); And
    A conductive metal layer having a thickness of 10,000 Angstroms or less; of
    An electric substrate made from a metal clad laminate comprising.
    [2" claim-type="Currently amended] The substrate of claim 1, wherein the substrate is selected from the group consisting of a printed wiring board, a laminate comprising at least one circuit trace, and at least one conductive via.
    [3" claim-type="Currently amended] The substrate of claim 1, further comprising an adhesive layer on the conductive metal layer on a surface opposite to the release agent layer.
    [4" claim-type="Currently amended] The substrate of claim 1 further comprising at least one semi-cured resin laminate layer attached to the conductive metal layer.
    [5" claim-type="Currently amended] (a) covering the surface of the carrier film and the carrier film,
    A metal clad laminate comprising a release agent layer comprising a water-soluble polymer that can be mechanically peeled from the carrier layer, and a conductive metal layer having a thickness of 10000 kPa or less, is bonded to the reinforced resin layer to form an electrical substrate. step;
    (b) removing the carrier film from the clad substrate;
    (c) introducing at least one via into the clad substrate;
    (d) forming a photoresist layer on the surface of the clad substrate;
    (e) exposing and developing the photoresist layer to expose the first portion of the conductive metal layer and cover the second portion of the conductive metal layer;
    (f) electroplating the exposed first conductive metal layer and at least one via with a conductive metal;
    (g) removing the resist layer from the metal clad laminate to expose the second conductive metal layer portion; And
    (h) flash etching the -laminate laminate to remove the exposed second conductive metal layer portion from the laminate;
    At least one circuit trace forming method on an electrical substrate using a metal-clad laminate.
    [6" claim-type="Currently amended] The method of claim 5 wherein the release agent layer is removed after the carrier film is removed in step (b) and before the vias are introduced into the substrate in step (c).
    [7" claim-type="Currently amended] 6. The method of claim 5 wherein the metal clad laminate comprises a second metal layer located between the conductive bundle layer and the reinforced resin layer.
    [8" claim-type="Currently amended] 8. The method of claim 7, wherein the second metal layer associated with the exposed second conductive metal layer portion is removed from the electrical substrate during the flash etch step (h).
    [9" claim-type="Currently amended] 8. The method of claim 7, wherein the metal clad laminate comprises an adhesive layer located between the second metal layer and the reinforcing resin layer.
    [10" claim-type="Currently amended] 10. The method of claim 9, wherein the adhesive layer is removed from the electrical substrate during the flash etch step (h).
    [11" claim-type="Currently amended] 10. The method of claim 9, wherein the adhesive layer is removed from the electrical substrate after the flash etching step (h).
    [12" claim-type="Currently amended] (a) a metal clad laminate comprising a carrier film, a release agent layer comprising a water-soluble polymer that covers the surface of the carrier film and can be mechanically peeled from the carrier film, and a conductive metal layer having a thickness of 10000 Pa or less; Adhering to the reinforced resin layer to form an electric substrate;
    (b) introducing at least one via into the clad substrate;
    (c) removing the carrier film from the clad substrate;
    (d) applying a photoresist layer to the surface of the clad substrate;
    (e) removing and developing the photoresist layer to expose the first conductive metal layer and cover the second conductive metal layer;
    (f) electroplating the exposed first conductive metal layer portions and at least one via with a conductive metal;
    (g) removing the resist layer from the metal clad laminate to expose the second conductive metal layer portion; And
    (h) flash etching the clad laminate to remove the exposed second conductive metal layer portion from the laminate;
    At least one circuit trace forming method on an electric substrate using a metal-clad laminate comprising a.
    [13" claim-type="Currently amended] 13. The method of claim 12, wherein the release layer is removed after the carrier layer is removed in step (c) and before the via is introduced into the substrate in step (d).
    [14" claim-type="Currently amended] 13. The method of claim 12, wherein the metal clad laminate comprises a second metal layer located between the conductive metal layer and the reinforcement resin layer.
    [15" claim-type="Currently amended] 15. The method of claim 14, wherein the second metal layer associated with the exposed second conductive metal layer portion is removed from the electrical substrate during the flash etch step (h).
    [16" claim-type="Currently amended] 15. The method of claim 14, wherein the metal clad laminate comprises an adhesive layer located between the second metal layer and the reinforcing resin layer.
    [17" claim-type="Currently amended] 17. The method of claim 16, wherein the adhesive layer is removed from the electrical substrate during the flash etch step (h).
    [18" claim-type="Currently amended] The method of claim 16, wherein the adhesive layer is removed from the electrical substrate after the flash etching step (h).
    [19" claim-type="Currently amended] The method of claim 12, wherein the via is introduced into the electrical substrate as a drill or a laser.
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    同族专利:
    公开号 | 公开日
    AU5485400A|2001-01-02|
    WO2000078107A1|2000-12-21|
    CN1370388A|2002-09-18|
    EP1190606A1|2002-03-27|
    JP2003501301A|2003-01-14|
    CA2374863A1|2000-12-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1999-06-14|Priority to US33261999A
    1999-06-14|Priority to US09/332,619
    2000-06-14|Application filed by 크리스 로저 에이치, 알라이드시그날 인코포레이티드
    2000-06-14|Priority to PCT/US2000/016220
    2002-02-08|Publication of KR20020011439A
    优先权:
    申请号 | 申请日 | 专利标题
    US33261999A| true| 1999-06-14|1999-06-14|
    US09/332,619|1999-06-14|
    PCT/US2000/016220|WO2000078107A1|1999-06-14|2000-06-14|High density substrate and methods for manufacturing same|
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